MLAB wiki

You've loaded an old revision of the document! If you save it, you will create a new version with this data.

FIXME **This page is not fully translated, yet. Please help completing the translation.**\\ //(remove this paragraph once the translation is finished)//

====== Analog-to-digital convertor - ADCdual01A ======

A fast two-channel analog-to-digital convertor. Input connector is a differential SATA connector - one for both analog channels. Output connector is a serial-parallel LVDS output to differential SATA connector:

===== Module interface =====

==== Sampling clock ====

The module requires connecting to a central clock, common to all digitising circuits - they would be derived through [[en:clkhub]] and from [[en:gpsdo|lokálního disciplinovaného oscilátoru]]. Their signal has to be brought to module by SATA cable to ENC SATA connector.

==== Data output ====

ADC’s data output assumes an established connection to FPGA, which would carry out the basic signal processing. Because the ADC has an adjustable bit width of output bus, the output connectors are again SATA. They are symmetrically divided in such way, that each receives one bit from every ADC channel.

There is also a possibility to connect through miniSAS-SATA cable - its connectors (on SATA side) are divided, according to a required sampling rate and the number of ADC, between individual ADC modules (increasing the bit width of bus lower the required bit speed of connection).

FPGA board thus needs miniSAS connector or several SATA connectors with several aggregated SATA cables.

===== Module application =====

One of the intended uses with for a system of [[en:aras|ARAS]] stations which has an unresolved problem of signal digitalisation from the antenna array.

Parameters important for the construction are:

* Dynamic range > 80 dB
  * Phase stability between individual channels
  * Noise
  * Sampling jitter < 100m

Currently, the problem is tackled on a professional level by proprietary digitising units (([[http://arxiv.org/abs/1305.3550|LOFAR]])) or more in amateur conditions by a system of multichannel sound cards (([[http://fringes.org/|Fringe Dwellers "Simple"]]))(([[http://radiojove.gsfc.nasa.gov/|Radio JOVE Project]])).

=== Choice of ADC ===

Choice of ADC influences a signal format fed into FPGA. There are several formats that are provided by available ADCs:

* <del>DDR LVDS</del>
  * <del>JEDEC 204B</del>
  * <del>JESD204A</del>
  * <del>Paralel LVDS</del>
  * <del>Serdes</del>
  * serial LVDS

So far, probably the most perspective is the usage of serial LVDS that requires the smallest number of differential signal pairs, making the whole construction simpler. (([[http://www.ti.com/lit/pdf/snaa110|Data Converter Serial LVDS Interface Improves Board Routing]]))

If we limit the choice of ADC by a requirement for serial LVDS output for each ADC channel individually, there will only be a few suitable circuits. Texas Instruments does not produce such fast 16 bit transducers at all and even their slower variants do not have LVDS output. Analog Devices, on the other hand, does not have ADC with serial data output with a bit with of interface smaller than 4bit/channel. 
We are left with a choice from the company Linear technology: 
either [[http://www.linear.com/product/LTC2271|LTC2271]]
or products from the [[http://www.linear.com/product/LTC2191|LTC2190-2195]] series.

As can be seen, the whole ADC series from Linear technology is more or less the same (the converters are even mutually interchangeable between the PCB), they only differ in sampling frequency and S/N ratio. The slowest one of them 
Jak je vidět, tak celá tato série ADC od Linear technology je víceméně stejná (dokonce jsou převodníky i
navzájem záměnné na stejně navrženém PCB), liší se pouze vzorkovací
frekvencí a poměrem S/N. Nejpomalejší z nich je však pro 20 MHz. Nejpomalejší
vzorkování na kterém ho lze provozovat je 5 MSPS. 
Všechny převodníky této kategorie jsou taky určitým způsobem
konfigurovatelné. A všechny ADC této kategorie (i jiné než od Linear Technology )mají pro konfiguraci rozhraní SPI.

===== Související stránky =====

* [[cs:adcoctospi|ADCoctoSPI]]
  * [[cs:aras|pokročilá radioastronomická stanice]]

===== Reference =====

==== Existující grabovací karty ====

* [[http://ultraviewcorp.com/displaynews.php?news_id=4|AD8-3000 High Speed Data Acquisition]]
  * [[http://www.muni.cz/research/projects/14245/web/comboi-adc|COMBOI-ADC]]
  * [[http://rtcmagazine.com/articles/view/101915|PX1500-2]]

Problematickými parametry těchto karet jsou zejména velmi vysoká cena, zbytečně vysoká vzorkovací frekvence a malý dynamický rozsah. A nebo velký dynamický rozsah ale naopak extrémně nízká vzorkovací frekvence.

Please fill all the letters into the box to prove you're human. V H V E V Please keep this field empty:

Edit summary

Note: By editing this page you agree to license your content under the following license: CC Attribution-Noncommercial-Share Alike 4.0 International