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— | en:adcdual [2018/12/18 15:23] – fluktuacia | ||
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+ | FIXME **This page is not fully translated, yet. Please help completing the translation.**\\ //(remove this paragraph once the translation is finished)// | ||
+ | |||
+ | |||
+ | ====== Analog-to-digital convertor - ADCdual01A ====== | ||
+ | |||
+ | A fast two-channel analog-to-digital convertor. Input connector is a differential SATA connector - one for both analog channels. Output connector is a serial-parallel LVDS output to differential SATA connector: | ||
+ | |||
+ | {{: | ||
+ | |||
+ | {{: | ||
+ | |||
+ | ===== Module interface ===== | ||
+ | |||
+ | ==== Sampling clock ==== | ||
+ | |||
+ | The module requires connecting to a central clock, common to all digitising circuits - they would be derived through [[en: | ||
+ | |||
+ | ==== Data output ==== | ||
+ | |||
+ | ADC’s data output assumes an established connection to FPGA, which would carry out the basic signal processing. Because the ADC has an adjustable bit width of output bus, the output connectors are again SATA. They are symmetrically divided in such way, that each receives one bit from every ADC channel. | ||
+ | |||
+ | There is also a possibility to connect through miniSAS-SATA cable - its connectors (on SATA side) are divided, according to a required sampling rate and the number of ADC, between individual ADC modules (increasing the bit width of bus lower the required bit speed of connection). | ||
+ | |||
+ | {{: | ||
+ | |||
+ | FPGA board thus needs miniSAS connector or several SATA connectors with several aggregated SATA cables. | ||
+ | |||
+ | ===== Module application ===== | ||
+ | |||
+ | One of the intended uses with for a system of [[en: | ||
+ | |||
+ | Parameters important for the construction are: | ||
+ | |||
+ | * Dynamic range > 80 dB | ||
+ | * Phase stability between individual channels | ||
+ | * Noise | ||
+ | * Sampling jitter < 100m | ||
+ | |||
+ | Currently, the problem is tackled on a professional level by proprietary digitising units (([[http:// | ||
+ | |||
+ | === Choice of ADC === | ||
+ | |||
+ | Choice of ADC influences a signal format fed into FPGA. There are several formats that are provided by available ADCs: | ||
+ | |||
+ | * < | ||
+ | * < | ||
+ | * < | ||
+ | * < | ||
+ | * < | ||
+ | * serial LVDS | ||
+ | |||
+ | So far, probably the most perspective is the usage of serial LVDS that requires the smallest number of differential signal pairs, making the whole construction simpler. (([[http:// | ||
+ | |||
+ | If we limit the choice of ADC by a requirement for serial LVDS output for each ADC channel individually, | ||
+ | We are left with a choice from the company Linear technology: | ||
+ | either [[http:// | ||
+ | or products from the [[http:// | ||
+ | |||
+ | As can be seen, the whole ADC series from Linear technology is more or less the same (the converters are even mutually interchangeable between the PCB), they only differ in sampling frequency and S/N ratio. The slowest one of them | ||
+ | Jak je vidět, tak celá tato série ADC od Linear technology je víceméně stejná (dokonce jsou převodníky i | ||
+ | navzájem záměnné na stejně navrženém PCB), liší se pouze vzorkovací | ||
+ | frekvencí a poměrem S/N. Nejpomalejší z nich je však pro 20 MHz. Nejpomalejší | ||
+ | vzorkování na kterém ho lze provozovat je 5 MSPS. | ||
+ | Všechny převodníky této kategorie jsou taky určitým způsobem | ||
+ | konfigurovatelné. A všechny ADC této kategorie (i jiné než od Linear Technology )mají pro konfiguraci rozhraní SPI. | ||
+ | |||
+ | ===== Související stránky ===== | ||
+ | |||
+ | * [[cs: | ||
+ | * [[cs: | ||
+ | |||
+ | ===== Reference ===== | ||
+ | |||
+ | ==== Existující grabovací karty ==== | ||
+ | |||
+ | * [[http:// | ||
+ | * [[http:// | ||
+ | * [[http:// | ||
+ | |||
+ | Problematickými parametry těchto karet jsou zejména velmi vysoká cena, zbytečně vysoká vzorkovací frekvence a malý dynamický rozsah. A nebo velký dynamický rozsah ale naopak extrémně nízká vzorkovací frekvence. | ||
en/adcdual.txt · Last modified: 2018/12/28 13:43 (external edit)