en:xvc_ft220x
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en:xvc_ft220x [2013/10/12 13:06] – [Xilinx Virtual JTAG Cable with USB FTDI chip FT220X] kaklik | en:xvc_ft220x [2013/10/12 13:43] – [Description of solution] kaklik | ||
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[[http:// | [[http:// | ||
- | This is set of software and electronic hardware created by [[cs: | + | It's a set of software and electronic hardware created by [[cs: |
[[http:// | [[http:// | ||
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===== Description of solution ===== | ===== Description of solution ===== | ||
- | To work with Xilinx FPGA hardware programmer | + | To work with Xilinx FPGA it is necessary to use a hardware programmer. It allows |
- | XILINX ISE development suite for FPGAs supports XVC protocol. This protocol | + | XILINX ISE development suite for FPGAs supports XVC protocol. This protocol |
==== Working principle ==== | ==== Working principle ==== | ||
- | Tento modul vytváří virtuální JTAG programovací kabel s obvodem FTDI FT220X s USB rozhraním na jedné straně a JTAG konektorem na straně druhé. Samotná komunikace s vývojovým prostředím probíhá přes TCP/IP sít, takže hradlové pole se může nacházet na jiném místě, než konstruktér vytvářející schéma. Celý systém je ilustrován na následujícím obrázku: | + | This module creates the virtual JTAG cable to the FPGA. This is based on FTDI FT220X USB interface chip and JTAG connector on its pins. Communication itself is realized over TCP/IP network thus of this FPGA can be located outside of developer |
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- | This module creates the virtual JTAG cable to the FPGA this is based on FTDI FT220X USB interface chip and JTAG connector on its pins. Communication itself is realized over TCP/IP network thus of this FPGA can be located outside of developer | + | |
{{ : | {{ : | ||
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==== Electronic construction ==== | ==== Electronic construction ==== | ||
- | The module contains minimum number of parts because majority of functionality components | + | The module contains minimum number of parts because majority of functionality components |
^ LED ^ Color ^ Function ^ | ^ LED ^ Color ^ Function ^ | ||
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==== System limitation ==== | ==== System limitation ==== | ||
- | This XVC system currently are not able to write to FPGA internal FLASH memory (due to software limitations). Then schema binary must be loaded after every power up cycle or [[cs: | + | This XVC system currently are not able to write to FPGA internal FLASH memory (due to software limitations). Then schema binary must be loaded after every power up cycle or [[en: |
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+ | ===== Related designs ===== | ||
+ | * [[en: |
en/xvc_ft220x.txt · Last modified: 2016/03/10 16:35 (external edit)