Differences

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--- en:xvc_ft220x [2013/10/12 13:07] – [Working principle] kaklik
+++ en:xvc_ft220x [2013/10/12 13:33] – [Xilinx Virtual JTAG Cable with USB FTDI chip FT220X] kaklik
@@ Line 4: / Line 4: @@
 [[http://www.mlab.cz/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/DOC/XVC_FT220X02A.cs.pdf|Original document XVC_FT220X02A]]
-This is set of software and electronic hardware created by [[cs:credits|MIHO]]. It is intended to obtain better accessible method of programming Xilinx FPGAs. More documents describing this method are available on
+It's a set of software and electronic hardware created by [[cs:credits|MIHO]]. It is intended to obtain a more accessible method of programming Xilinx FPGAs. More documents describing this method are available on
 [[http://www.mlab.cz/Server/GenIndex/GenIndex.php?path=%2FModules%2FCPLD_FPGA%2FXILINX_XVC&lang=cs|MLAB documents list page]].
@@ Line 16: / Line 16: @@
 ==== Working principle ====
-This module creates the virtual JTAG cable to the FPGA this is based on FTDI FT220X USB interface chip and JTAG connector on its pins. Communication itself is realized over TCP/IP network thus of this FPGA can be located outside of developer work place. The whole process is illustrated on following picture
+This module creates the virtual JTAG cable to the FPGA. This is based on FTDI FT220X USB interface chip and JTAG connector on its pins. Communication itself is realized over TCP/IP network thus of this FPGA can be located outside of developer working place. The whole process is illustrated on following picture:
 {{ :cs:fpga:schemacyklu_small.png?direct&500 |}}
@@ Line 22: / Line 22: @@
 ==== Electronic construction ====
-The module contains minimum number of parts because majority of functionality components is resolved by control software. The most important for user are some connectors and indicating LEDs with following meaning:
+The module contains minimum number of parts because majority of functionality components are included in a  control software. So the most important for user are some connectors and indicating LEDs with following meaning:
 ^ LED ^ Color ^ Function ^
@@ Line 48: / Line 48: @@
 ==== System limitation ====
-This XVC system currently are not able to write to FPGA internal FLASH memory (due to software limitations). Then schema binary must be loaded after every power up cycle or [[cs:jtagft2232v|JTAGFT2232V02A]] programmer must be used.
+This XVC system currently are not able to write to FPGA internal FLASH memory (due to software limitations). Then schema binary must be loaded after every power up cycle or [[en:jtagft2232v|JTAGFT2232V02A]] programmer must be used.
+===== Related designs =====
+  * [[en:s3an|S3AN01A]] - FPGA school board