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en:xvc_ft220x [2013/10/12 13:17] – [Working principle] kakliken:xvc_ft220x [2013/10/12 13:33] – [Xilinx Virtual JTAG Cable with USB FTDI chip FT220X] kaklik
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 [[http://www.mlab.cz/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/DOC/XVC_FT220X02A.cs.pdf|Original document XVC_FT220X02A]] [[http://www.mlab.cz/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/DOC/XVC_FT220X02A.cs.pdf|Original document XVC_FT220X02A]]
  
-This is set of software and electronic hardware created by [[cs:credits|MIHO]]. It is intended to obtain better accessible method of programming Xilinx FPGAs. More documents describing this method are available on +It's a set of software and electronic hardware created by [[cs:credits|MIHO]]. It is intended to obtain a more accessible method of programming Xilinx FPGAs. More documents describing this method are available on 
 [[http://www.mlab.cz/Server/GenIndex/GenIndex.php?path=%2FModules%2FCPLD_FPGA%2FXILINX_XVC&lang=cs|MLAB documents list page]]. [[http://www.mlab.cz/Server/GenIndex/GenIndex.php?path=%2FModules%2FCPLD_FPGA%2FXILINX_XVC&lang=cs|MLAB documents list page]].
  
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 ==== Electronic construction ==== ==== Electronic construction ====
  
-The module contains minimum number of parts because majority of functionality components is resolved by control software. The most important for user are some connectors and indicating LEDs with following meaning:+The module contains minimum number of parts because majority of functionality components are included in a  control software. So the most important for user are some connectors and indicating LEDs with following meaning:
  
 ^ LED ^ Color ^ Function ^ ^ LED ^ Color ^ Function ^
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 ==== System limitation ==== ==== System limitation ====
  
-This XVC system currently are not able to write to FPGA internal FLASH memory (due to software limitations). Then schema binary must be loaded after every power up cycle or [[cs:jtagft2232v|JTAGFT2232V02A]] programmer must be used.+This XVC system currently are not able to write to FPGA internal FLASH memory (due to software limitations). Then schema binary must be loaded after every power up cycle or [[en:jtagft2232v|JTAGFT2232V02A]] programmer must be used.
  
 +===== Related designs =====
 +
 +  * [[en:s3an|S3AN01A]] - FPGA school board
en/xvc_ft220x.txt · Last modified: 2016/03/10 16:35 (external edit)