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en:xvc_ft220x [2013/10/12 14:05] – [Use of XVC module] kakliken:xvc_ft220x [Unknown date] (current) – external edit (Unknown date) 127.0.0.1
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-[[http://www.mlab.cz/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/DOC/XVC_FT220X02A.cs.pdf|Original document XVC_FT220X02A]]+[[http://www.mlab.cz/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/DOC/XVC_FT220X02A.cs.pdf|Original document XVC_FT220X02A]], [[http://www.ust.cz/shop/product_info.php?products_id=237|UST store]]
  
 It's a set of software and electronic hardware created by [[cs:credits|MIHO]]. It is intended to obtain a more accessible method of programming Xilinx FPGAs. More documents describing this method are available on  It's a set of software and electronic hardware created by [[cs:credits|MIHO]]. It is intended to obtain a more accessible method of programming Xilinx FPGAs. More documents describing this method are available on 
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 === Service software === === Service software ===
  
-The XVC module is controlled by OpenSource software [[cs:xvc_software|mlab_xvcd]]. This utility is fully supported in windows operating system Linux version is in development stage.+The XVC module is controlled by OpenSource software [[cs:xvc_software|mlab_xvcd]]. This utility is fully supported by Windows operating system. Linux version is currently under development.
  
 === Use of XILINX ChipScope === === Use of XILINX ChipScope ===
  
-ChipScope is valuable tool enabling the monitoring of internal octions in FPGA by integrated logical analyzer. It can be used in combination with XVC system. +ChipScope is a valuable tool enabling the monitoring of internal actions in FPGA by integrated logical analyzer. It can be used in combination with the XVC system. 
  
-==== System limitation ====+==== System limitations ====
  
-This XVC system currently are not able to write to FPGA internal FLASH memory (due to software limitations). Then schema binary must be loaded after every power up cycle or [[en:jtagft2232v|JTAGFT2232V02A]] programmer must be used.+The XVC system is currently not able to write to FPGA internal FLASH memory (due to software limitations). Therefore the binary scheme must be loaded after every power up cycle or a [[en:jtagft2232v|JTAGFT2232V02A]] programmer must be used.
  
 ===== Related designs ===== ===== Related designs =====
  
   * [[en:s3an|S3AN01A]] - FPGA school board   * [[en:s3an|S3AN01A]] - FPGA school board
en/xvc_ft220x.1381586725.txt.gz · Last modified: 2013/10/12 14:05 (external edit)