en:adcdual
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- | FIXME **This page is not fully translated, yet. Please help completing the translation.**\\ //(remove this paragraph once the translation is finished)// | ||
- | ====== Analog-to-digital convertor - ADCdual01A ====== | ||
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- | A fast two-channel analog-to-digital convertor. Input connector is a differential SATA connector - one for both analog channels. Output connector is a serial-parallel LVDS output to differential SATA connector: | ||
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- | {{: | ||
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- | {{: | ||
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- | ===== Module interface ===== | ||
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- | ==== Sampling clock ==== | ||
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- | The module requires connecting to a central clock, common to all digitising circuits - they would be derived through [[en: | ||
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- | ==== Data output ==== | ||
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- | ADC’s data output assumes an established connection to FPGA, which would carry out the basic signal processing. Because the ADC has an adjustable bit width of output bus, the output connectors are again SATA. They are symmetrically divided in such way, that each receives one bit from every ADC channel. | ||
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- | There is also a possibility to connect through miniSAS-SATA cable - its connectors (on SATA side) are divided, according to a required sampling rate and the number of ADC, between individual ADC modules (increasing the bit width of bus lower the required bit speed of connection). | ||
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- | {{: | ||
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- | FPGA board thus needs miniSAS connector or several SATA connectors with several aggregated SATA cables. | ||
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- | ===== Module application ===== | ||
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- | One of the intended uses with for a system of [[en: | ||
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- | Parameters important for the construction are: | ||
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- | * Dynamic range > 80 dB | ||
- | * Phase stability between individual channels | ||
- | * Noise | ||
- | * Sampling jitter < 100m | ||
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- | Currently, the problem is tackled on a professional level by proprietary digitising units (([[http:// | ||
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- | === Choice of ADC === | ||
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- | Choice of ADC influences a signal format fed into FPGA. There are several formats that are provided by available ADCs: | ||
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- | * < | ||
- | * < | ||
- | * < | ||
- | * < | ||
- | * < | ||
- | * serial LVDS | ||
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- | So far, probably the most perspective is the usage of serial LVDS that requires the smallest number of differential signal pairs, making the whole construction simpler. (([[http:// | ||
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- | If we limit the choice of ADC by a requirement for a serial LVDS output for each ADC channel individually, | ||
- | We are left with a choice from the company Linear technology: | ||
- | either [[http:// | ||
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- | As can be seen, the whole ADC series from Linear technology is more or less the same (the converters are even mutually interchangeable between the same PCB layout), they only differ in sampling frequency and S/N ratio. The slowest one of them can be used for sampling rate of 20 MHz. The slowest sampling rate that it is able to carried out is 5 MSPS. All converters from this category are more or less configurable and all ADCs’ (even others than made by Linear Technology) have SPI interface for configuration. | ||
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- | ===== Related sites ===== | ||
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- | * [[en: | ||
- | * [[en: | ||
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- | ===== Refferences ===== | ||
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- | ==== Existing grabbing cards ==== | ||
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- | * [[http:// | ||
- | * [[http:// | ||
- | * [[http:// | ||
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- | There are several problems with these devices - especially their high price, unnecessarily high sampling rates and small dynamic range or, on the contrary, large dynamic range, but extremely low sampling rates. |
en/adcdual.txt · Last modified: 2018/12/28 13:43 (external edit)