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+======  Differential input Clock divider CLKDIV01A ======
+{{ :cs:modules:measuring:clkdiv01a_top_big.jpg?direct&300 |}}
+Multiple division ratios can be selected by jumpers. Possible division ratios are: (÷1, ÷2, ÷4, ÷8) or (÷2, ÷4, ÷8, ÷16) every output is synchronous each other. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state.