en:clkhub
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| en:clkhub [2013/07/25 17:08] – created fluktuacia | en:clkhub [2013/07/26 08:31] – [__Clock divider__ CLKHUB01A] kaklik | ||
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| The module should be able to generate clock signals with high phase accuracy. The main purpose of this circuit is the generation of clocks for fast ADCs, that are characterized by their high demands for phase noise and signal quality in general. The module is currently not finished. The suitable VCO for the phase-locked loop of the AD9510 circuit is not yet chosen. | The module should be able to generate clock signals with high phase accuracy. The main purpose of this circuit is the generation of clocks for fast ADCs, that are characterized by their high demands for phase noise and signal quality in general. The module is currently not finished. The suitable VCO for the phase-locked loop of the AD9510 circuit is not yet chosen. | ||
en/clkhub.txt · Last modified: 2013/07/26 08:31 (external edit)