Differences

This shows you the differences between two versions of the page.

--- en:xvc_ft220x [2013/10/12 13:04] – [System limitation] kaklik
+++ en:xvc_ft220x [Unknown date] (current) – external edit (Unknown date) 127.0.0.1
@@ Line 2: / Line 2: @@
-[[http://www.mlab.cz/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/DOC/XVC_FT220X02A.cs.pdf|Original documents XVC_FT220X02A]]
+[[http://www.mlab.cz/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/DOC/XVC_FT220X02A.cs.pdf|Original document XVC_FT220X02A]], [[http://www.ust.cz/shop/product_info.php?products_id=237|UST store]]
-It is set of software and electronic hardware created by [[cs:credits|MIHO]]. It is intended to obtain better available method of programming Xilinx FPGAs. More documents describing this method are available on
+It's a set of software and electronic hardware created by [[cs:credits|MIHO]]. It is intended to obtain a more accessible method of programming Xilinx FPGAs. More documents describing this method are available on
-[[http://www.mlab.cz/Server/GenIndex/GenIndex.php?path=%2FModules%2FCPLD_FPGA%2FXILINX_XVC&lang=cs|MLAB list page]].
+[[http://www.mlab.cz/Server/GenIndex/GenIndex.php?path=%2FModules%2FCPLD_FPGA%2FXILINX_XVC&lang=cs|MLAB documents list page]].
 ===== Description of solution =====
-To work with Xilinx FPGA hardware programmer is needed. It allows load of schema binary in to the chip. This method can be realized  by connecting the FPGA chip to the JTAG interface device.
+To work with Xilinx FPGA it is necessary to use a hardware programmer. It allows a loading of a binary scheme into the chip. This can be realized by connecting the FPGA chip to the JTAG interface device.
-XILINX ISE development suite for FPGAs supports XVC protocol. This protocol allow remote TCP/IP connection to the JTAG device which is connected to the FPGA chip at the remote end.
+XILINX ISE development suite for FPGAs supports XVC protocol. This protocol allows a remote TCP/IP connection to the JTAG device which is connected to the FPGA chip at the remote end.
-==== Working principle ====
+==== Operating principle ====
-Tento modul vytváří virtuální JTAG programovací kabel s obvodem FTDI FT220X s USB rozhraním na jedné straně a JTAG konektorem na straně druhé. Samotná komunikace s vývojovým prostředím probíhá přes TCP/IP sít, takže hradlové pole se může nacházet na jiném místě, než konstruktér vytvářející schéma. Celý systém je ilustrován na následujícím obrázku:
+This module creates a virtual JTAG cable to the FPGA. This is based on joining of the FTDI FT220X USB interface chip pins with JTAG connector. Communication itself is realized over TCP/IP network and thus the FPGA can be located outside of the developer working place. The whole process is illustrated on following picture:
-This module creates the virtual JTAG cable to the FPGA this is based on FTDI FT220X USB interface chip and JTAG connector on its pins. Communication itself is realized over TCP/IP network thus of this FPGA can be located outside of developer work place. The whole process is illustrated on following picture
 {{ :cs:fpga:schemacyklu_small.png?direct&500 |}}
-==== Electronic construction ====
+==== Electronics construction ====
+The module contains a minimum number of parts because a majority of a communication protocol components are included in a control software. For users, the most important parts of the device are several connectors and indicator LEDs with the following meaning:
-The module contains minimum number of parts because majority of functionality components is resolved by control software. The most important for user are some connectors and indicating LEDs with following meaning:
 ^ LED ^ Color ^ Function ^
-|TGT D1 | Red | Indicate voltage on JTAG programming connector |
+|TGT D1 | Red | Indicates a voltage on JTAG programming connector |
 |ACT D2 | Green | Data transmission activity |
-|USB D3 | Red | Indicates USB power voltage |
+|USB D3 | Red | Indicates an USB power voltage |
-There are two jumpers on the board of module: Jumper J3 marked as VIO PWR - this jumper selects JTAG working voltage (Internal 3.3 V regulated by FTDI chip or TGT voltage from JTAG connector).
+There are two jumpers on the board of the module: Jumper J3 marked as VIO PWR - this jumper selects JTAG working voltage (Internal 3.3 V regulated by FTDI chip or TGT voltage from the JTAG connector).
-Jumper 4 provides +5V power to target device from USB.
+Jumper 4 provides +5V power to the target device from USB.
-==== Use of XVC module ====
+==== The use of XVC module ====
-For use of this module XILINX development suite with iMPACT software is needed. In addition you need mlab_xvcd service utility.
+To use this module, a XILINX development suite with iMPACT software is needed. In addition to this you need a mlab_xvcd service utility.
 === Service software ===
-The XVC module is controlled by OpenSource software [[cs:xvc_software|mlab_xvcd]]. This utility is fully supported in windows operating system Linux version is in development stage.
+The XVC module is controlled by OpenSource software [[cs:xvc_software|mlab_xvcd]]. This utility is fully supported by Windows operating system. Linux version is currently under development.
 === Use of XILINX ChipScope ===
-ChipScope is valuable tool enabling the monitoring of internal octions in FPGA by integrated logical analyzer. It can be used in combination with XVC system.
+ChipScope is a valuable tool enabling the monitoring of internal actions in FPGA by integrated logical analyzer. It can be used in combination with the XVC system.
+==== System limitations ====
-==== System limitation ====
+The XVC system is currently not able to write to FPGA internal FLASH memory (due to software limitations). Therefore the binary scheme must be loaded after every power up cycle or a [[en:jtagft2232v|JTAGFT2232V02A]] programmer must be used.
-This XVC system currently are not able to write to FPGA internal FLASH memory (due to software limitations). Then schema binary must be loaded after every power up cycle or [[cs:jtagft2232v|JTAGFT2232V02A]] programmer must be used.
+===== Related designs =====
+  * [[en:s3an|S3AN01A]] - FPGA school board